1. Field of the Invention
The invention relates in general to a vertical channel memory, to a manufacturing method thereof therefor and to an operating method using the same. More particularly the invention relates to a vertical channel memory with high scalability, to a manufacturing method therefor and to an operating method using the same.
2. Description of the Related Art
Along with the advance in manufacturing technology for semiconductor devices, the resolution of current semiconductor elements has reached nano levels. Take the memory for example, the length of the gate and the element pitch are further reduced. With sizes near the resolution limits of lithography, the manufactured transistor element still has the problems of electrostatic discharge (ESD), leakage, and reduction in electron mobility, and is apt to short channel effect and drain induced barrier lowering (DIBL) effect. Therefore, the double-gate vertical channel transistor and the tri-gate vertical channel transistor capable of providing higher packing density, better carrier transport and device scalability, such as fin field effect transistor (FinFET), have become transistor structures with great potential.
The FinFET has a vertical channel, and can form channels on two vertical surfaces and control the connection of current by double-gate or tri-gate structures, hence having better efficiency than conventional planar channel transistors.
The manufacturing of FinFET elements with high resolution still requires expensive and advanced manufacturing processes by photolithography or E-beam. However, the throughput of these advanced manufacturing processes is difficult to increase and is disadvantageous to large-scale production. One of the present manufacturing methods is etching a channel first and then the line width of the channel is reduced by oxidation. However, the element formed according to such method has poor uniformity and the quality is difficult to control.